Method and system for operating gallium nitride electronics

ABSTRACT

An electronic circuit comprising a driver and a main transistor are provided. The driver may include a bias voltage generator, a supplementary transistor, and an output driver. The bias voltage generator may be configured to receive a voltage input and generate a biased voltage output based on the voltage input. The supplementary transistor may have a gate coupled to the biased voltage output of the bias voltage generator, and a source of the supplementary transistor providing a current to the bias voltage generator. The output driver may be configured to receive the biased voltage output from the bias voltage generator and the voltage input, receive the voltage input, and output a drive voltage. The main transistor of the electronic circuit may have a gate, a coupled to the drive voltage, and a drain coupled to a drain of the supplementary transistor.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 14/045,708,filed Oct. 3, 2013, entitled “METHOD AND SYSTEM FOR OPERATING GALLIUMELECTRONICS,” (now allowed), the disclosure of which is incorporatedherein by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

Power electronics are widely used in a variety of applications. Powerelectronic devices are commonly used in circuits to modify the form ofelectrical energy, for example, from AC to DC, DC to DC, and from onevoltage level to another. Such devices can operate over a wide range ofpower levels, from milliwatts in mobile devices to hundreds of megawattsin high voltage power transmission systems, and at increasingly highfrequencies for modern electronic applications. Despite the progressmade in power electronics, there is a need in the art for improvedelectronics systems for achieving higher power conversion efficienciesand methods of operating the same.

SUMMARY OF THE INVENTION

The present invention relates generally to electronic devices. Morespecifically, the present invention relates to a transistor driver usinggallium nitride (GaN) electronics. Merely by way of example, theinvention has been applied to methods and systems for using aconventional insulated-gate bipolar transistor (IGBT) gate driver inconjunction with a GaN transistor driver and a GaN transistor. Themethods and techniques can be applied to a variety of semiconductordevices, such as metal-oxide-semiconductor field-effect transistors(MOSFETs), bipolar transistors (BJTs, HBTs), diodes, and the like.

According to an embodiment of the present invention, an electronicdevice is provided. The electronic device can be an electronic circuitcomprising a driver and a main transistor. The driver may include a biasvoltage generator, a supplementary transistor, and an output driver. Thebias voltage generator may be configured to receive a voltage input andgenerate a biased voltage output based on the voltage input. Thesupplementary transistor may have a gate, a drain, and a source, inwhich the gate of the supplementary transistor is coupled to the biasedvoltage output of the bias voltage generator, and the source of thesupplementary transistor provide a current to the bias voltagegenerator. The output driver may be configured to receive the biasedvoltage output from the bias voltage generator and the voltage input,receive the voltage input, and output a drive voltage. The maintransistor of the electronic circuit may have a gate, a drain, and asource, in which the gate of the main transistor is coupled to the drivevoltage, and the drain of the main transistor is coupled to the drain ofthe supplementary transistor.

According to another embodiment of the present invention, a method ofoperating a GaN JFET is provided. The GaN JFET may receive an inputvoltage and generate a biased voltage output based on the input voltage.The method further includes monitoring a current of a supplementarytransistor to provide a current value and receiving, at an output drive,the biased voltage output, the current value, and the input voltage.Additionally, the method may involve generating an output drive voltagebased on the biased voltage output, the current value, and the inputvoltage, and providing, to the GaN JFET, the output drive voltage.

Numerous benefits are achieved by way of the present invention overconventional techniques. For example, embodiments of the presentinvention decrease the physical size of the power device because of theproperties of using GaN devices as opposed to typical MOSFETs and BJTs.Some embodiments of the present invention achieve an increase inswitching frequency and reduced heat through using a combination ofadvanced circuit topologies and state-of-the-art power devices made fromGaN materials.

Furthermore, embodiments of the invention provide a co-packaged GaNdriver and electronic devices that provide more cost-effective solutionsthan conventional techniques. For example, the GaN driver and transistordescribed herein co-package a GaN driver circuit and a transistor, suchthat only one electronic package is utilized. Co-packaging GaN devicesalso results in easier assembly of the electronic packages, less boardspace, and therefore less cost for the board and its enclosure. Theseand other embodiments of the present invention, along with many of itsadvantages and features, are described in more detail in conjunctionwith the text below and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic diagram of an IGBT Gate Driver inconjunction with a GaN transistor circuit according to an embodiment ofthe present invention.

FIG. 2 is a simplified schematic diagram illustrating elements of a GaNtransistor circuit according to an embodiment of the present invention.

FIG. 3 is an exemplary schematic diagram illustrating devices suitablefor use in elements of a GaN transistor circuit according to anembodiment of the present invention.

FIG. 4 is a simplified flowchart illustrating a method of using an IGBTgate driver in conjunction a GaN transistor according to an embodimentof the present invention.

FIG. 5 illustrates the behavior of the exemplary schematic diagram ofFIG. 3 according to an embodiment of the invention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

The present invention relates generally to electronic devices. Morespecifically, the present invention relates to a transistor driver usinggallium nitride (GaN) electronics. Merely by way of example, theinvention has been applied to methods and systems for using aconventional insulated-gate bipolar transistor (IGBT) gate driver inconjunction with a GaN transistor driver and a GaN transistor. Themethods and techniques can be applied to a variety of semiconductordevices, such as metal-oxide-semiconductor field-effect transistors(MOSFETs), bipolar transistors (BJTs, HBTs), diodes, and the like.

GaN-based electronic devices are undergoing rapid development, andgenerally are expected to outperform competitors in silicon (Si) andsilicon carbide (SiC). Desirable properties associated with GaN andrelated alloys and heterostructures include high bandgap energy forvisible and ultraviolet light emission, favorable transport properties(e.g., high electron mobility and saturation velocity), a high breakdownfield, and high thermal conductivity. In particular, electron mobility,μ, is higher than competing materials for a given background dopinglevel, N. This provides low resistivity, ρ, because resistivity isinversely proportional to electron mobility, as provided by equation(1):

$\begin{matrix}{{\rho = \frac{1}{q\; \mu \; N}},} & (1)\end{matrix}$

where q is the elementary charge.

Another superior property provided by GaN materials, includinghomoepitaxial GaN layers on bulk GaN substrates, is high criticalelectric field for avalanche breakdown. A high critical electric fieldallows a larger voltage to be supported over smaller length, L, than amaterial with a lower critical electric field. A smaller length forcurrent to flow together with low resistivity give rise to a lowerresistance, R, than other materials, since resistance can be determinedby equation (2):

$\begin{matrix}{{R = \frac{\rho \; L}{A}},} & (2)\end{matrix}$

where A is the cross-sectional area of the channel or current path.

An insulated-gate bipolar transistor (IGBT) is a three-terminal powersemiconductor device that may be used as an electronic switch.Typically, IGBT devices are fabricated on silicon substrates and owingto the material properties of silicon (not being a wide bandgapsemiconductor), a large thickness of silicon is needed to block a givenreverse voltage across the device. Additionally owing to the muchsmaller mobility of silicon compared to GaN, large device areas areneeded in order to achieve a certain current rating. This tends toconsume a large surface area on the semiconductor, which in turnincreases device capacitance and hence IGBTs can only be switched atslower frequencies <100 kHz to minimize switching losses

Advantages in using IGBTs as electronic switches at lower frequenciesincludes high efficiency, which may be utilized in various electronicapplications, including Variable-Frequency Drives (VFDs), electric cars,trains, variable speed refrigerators, air-conditioners and even stereosystems with switching amplifiers. In switching applications for modernelectronic devices, the pulse repetition rates may reach frequencies atleast ten times the highest audio frequency handled by an analog audioamplifier. Thus, with the advancement of modern electronics, the powerapplications for high-speed, low-power, and low-cost electronic switchesmay be greatly increased.

The superior properties of GaN can give rise to improved semiconductordevices, especially power switching semiconductor devices that utilizedvertical architectures. Vertical semiconductor devices, in comparisonwith lateral devices, utilize a smaller surface area to achieve the sameperformance (i.e., forward current conduction capability) as lateraldevices. Vertical semiconductor devices have electrical contacts on boththe top surface of the semiconductor and on the bottom surface, orbackside, such that current flows vertically between the electricalcontacts. Vertical power devices are vertical semiconductor devices thatcan be utilized in high power and/or high voltage applications, such aspower electronics.

IGBT circuits are typically driven by an IGBT driver. Embodiments of thepresent invention utilize conventional IGBT drivers to drive circuitsutilizing GaN-based electronics. As described herein, the GaN transistorcircuit provided according to embodiments of the present inventioncomprises a GaN JFET driver driving a main GaN JFET co-packaged togethersuch that the GaN transistor circuit may be utilized in conjunction withan IGBT driver, effectively replacing a three-terminal IGBT. For a givenvoltage and current rating, GaN power devices may be significantlysmaller and more compact than their silicon counterparts. For example, a600 V, 5 A GaN power device may have a surface area that is 100 timessmaller than a 600 V, 5 A silicon IGBT. Vertical GaN power devices mayalso be operated at much higher frequencies (e.g., 500 kHz-20 MHz)compared to silicon IGBTs (e.g., up to 100 kHz) without an increase inpower loss. Embodiments of the present invention enable operation athigh frequencies with increased performance and reduced switchinglosses.

The capacitance of a power semiconductor device generally scales witharea, so GaN power devices generally have much lower capacitance thansimilarly rated silicon power devices. Package-related capacitance alsoscales with size, so the electronic package-related capacitance is alsogreatly reduced as a result of smaller package sizes associated with GaNcircuits. These lower capacitances provide greatly reduced switchinglosses for GaN power devices in comparison to similarly rated siliconpower devices. Due to their small size, GaN devices may be co-packagedclosely together, and parasitic inductance, resistance, and capacitanceassociated with interconnections between devices may be substantiallyreduced as the interconnection (e.g., current path) between thesedevices is made through a highly-conductive leadframe. Reducing theseparasitic inductances greatly reduces electromagnetic interference(EMI), especially at high switching frequencies, and also reduces theover-voltage stress on the power semiconductor devices and other powerelectronic circuit elements. As a result, power electronics according toembodiments of the invention provide benefits and advantages such asfaster switching, lower power loss, and less EMI than achieved withconventional approaches.

FIG. 1 is a simplified schematic diagram of an IGBT Gate Driver inconjunction with a GaN transistor circuit according to an embodiment ofthe present invention. As illustrated in FIG. 1, an IGBT gate driver 126is used to drive a three-terminal GaN transistor circuit 120, includinga GaN JFET driver 122, and a GaN JFET 124 (which may also be referred toas a main JFET). The GaN transistor circuit 120 comprises threeterminals that correspond to the three terminals that would be providedby a conventional IGBT. The three-terminal GaN transistor circuit 120comprises three terminals: A2 at the input of the GaN JFET driver 122(which is coupled to the gate node of JFET 124), B2 at the drain node ofJFET 124, and C2 at the source node of JFET 124. Processes for thefabrication of a vertical GaN transistor suitable for use as GaN JFET124 are provided in commonly assigned U.S. Patent ApplicationPublication No. 2013/0112985, published on May 9, 2013, the disclosureof which is hereby incorporated by reference.

Examples of device structures that can be utilized in GaN JFET 124,which can also be referred to as a GaN power transistor, include a firstgallium nitride layer that is coupled to a substrate. In someembodiments, the substrate is a gallium nitride substrate.

In some embodiments, first gallium nitride layer can include anepitaxially grown gallium nitride layer, e.g., GaN that has n-typeconductivity. First gallium nitride layer can serve as a drift regionand therefore can be a relatively low-doped material. For example, firstgallium nitride layer can have an n-conductivity type, with dopantconcentrations ranging from 1×10¹⁴ cm⁻³ to 1×10¹⁸ cm⁻³. Furthermore, thedopant concentration can be uniform, or can vary, for example, as afunction of the thickness of the drift region. In some embodiments,n-type dopants can include silicon, oxygen, selenium, tellurium, or thelike.

The thickness of first gallium nitride layer can also varysubstantially, depending on the desired functionality. Homoepitaxialgrowth can enable first gallium nitride layer to be grown far thickerthan heteroepitaxial GaN layers formed on non-GaN substrates.Thicknesses can vary between 0.5 μm and 100 μm, for example. In someembodiments thicknesses are greater than 5 μm. Resulting parallel planebreakdown voltages for GaN power transistor can vary depending on theembodiment. Some embodiments provide for breakdown voltages of at least100 V, 300 V, 600 V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

A second gallium nitride layer can be epitaxially grown over the firstgallium nitride layer. The second gallium nitride layer, from which edgetermination structures may be eventually formed, can have a conductivitytype different than first gallium nitride layer. For instance, if firstgallium nitride layer is formed from an n-type GaN material, secondgallium nitride layer may be formed from a p-type GaN material, and viceversa. In some embodiments, second gallium nitride layer is used to formthe edge termination structures and is a continuous regrowth overportions of first gallium nitride layer with other portions of thestructure, such as regions of other semiconductor devices, characterizedby reduced or no growth as a result of the presence of a regrowth mask(not shown). One of ordinary skill in the art would recognize manyvariations, modifications, and alternatives.

The thickness of second gallium nitride layer can vary, depending on theprocess used to form the layer and the device design. In someembodiments, the thickness of second gallium nitride layer 108 isbetween 0.1 μm and 5 μm.

Second gallium nitride layer can be highly doped, for example in a rangefrom about 5×10¹⁷ cm⁻³ to about 1×10¹⁹ cm⁻³. Additionally, as with otherepitaxial layers, the dopant concentration of second gallium nitridelayer can be uniform or non-uniform as a function of thickness. In someembodiments, the dopant concentration increases with thickness, suchthat the dopant concentration is relatively low near first galliumnitride layer and increases as the distance from first gallium nitridelayer increases. Such embodiments provide higher dopant concentrationsat the top of second gallium nitride layer where metal contacts can besubsequently formed. Other embodiments utilize heavily doped contactlayers to form Ohmic contacts.

One method of forming the second gallium nitride layer, and other layersdescribed herein, can be through a regrowth process that uses an in-situetch and diffusion preparation processes. These preparation processesare described more fully in U.S. Patent Application Publication No.2013/0032814, published on Feb. 7, 2013, the disclosure of which ishereby incorporated by reference in its entirety. The second galliumnitride layer can be used to form the gate region of the vertical GaNpower transistor.

The second gallium nitride layer/gate region can include a continuousregion and one or more finger-like projections. Together, the continuousregion and projections form the gate region of the GaN vertical powertransistor. A gate electrode is disposed over continuous region andcoupled to gate region via gate contacts. In some embodiments, gateelectrode can include metals such as scandium, nickel, platinum,palladium, silver, gold, copper, aluminum, etc. and alloys thereof. Insome embodiments, gate electrode can be a multi-layered structure.

In one embodiment, at least some portions of the gate region may alsoinclude a low resistance layer that may be disposed on top of the secondgallium nitride layer. This low resistance layer may include a metalsuch as scandium, platinum, palladium, nickel, or other suitablematerials. The purpose of this layer is to reduce the lateral resistancefrom gate electrode to various locations on the gate region, which maybe advantageous to reduce the distributed gate resistance of verticalpower transistor and, thus, improve the switching performance.

Although some embodiments are discussed in terms of a GaN substrate,embodiments of the present invention are not limited to GaN substrates.Other III-V materials, in particular, III-nitride materials, areincluded within the scope of the present invention and can besubstituted not only for the illustrative GaN substrate, but also forother GaN-based layers and structures described herein. As examples,binary III-V (e.g., III-nitride) materials, ternary III-V (e.g.,III-nitride) materials such as InGaN and AlGaN, and quaternary III-V(e.g., III-nitride) materials such as AlInGaN are also included withinthe scope of the present invention.

The GaN power transistor may utilize an n-type drift layer that is grownon top of an n-type substrate. However, the present invention is notlimited to this particular configuration. In other embodiments,substrates with p-type doping can be utilized. Additionally, embodimentscan use materials having an opposite conductivity type to providedevices with different functionality. Thus, although some embodimentsdescribed herein include n-type GaN epitaxial layer(s) doped withsilicon, other n-type dopants may be used, such as Ge, Se, S, O, Te, andthe like. In other embodiments, highly or lightly doped material, p-typematerial, material doped with dopants such as Mg, Ca, Be, and the likecan also be used. The substrates discussed herein can include a singlematerial system or multiple material systems including compositestructures of multiple layers. One of ordinary skill in the art wouldrecognize many variations, modifications, and alternatives.

A key feature of the present invention is that a GaN JFET can be drivendirectly by a conventional IGBT Gate Driver 126. Large selections ofIGBT gate drivers are commercially available and widely used to drivesilicon IGBTs. The present invention provides a three-terminalreplacement for a silicon IGBT that can be directly driven by a standardIGBT Gate Driver with no need for any additional circuitry.

In FIG. 1, at node A2, an input voltage is received from the IGBT GateDriver 126. This input voltage may be any standard voltage waveform thatis generated by the IGBT Gate Driver 126. By way of example, the inputvoltage may be a square wave with a low level of −15V and a high levelof +15V. Because the construction of a GaN JFET may be different thanthe construction of a conventional silicon-based transistor, there maybe a limitation on how much voltage that can be applied to the gate nodeof the GaN JFET 124.

In a typical IGBT circuit, the gate of the IGBT may be capable ofhandling high voltage (e.g., +15/−15 V) input from the IGBT gate driver.According to embodiments of the present invention, the gate node of theJFET 124 may be limited to a voltage range that may be smaller than theoutput of IGBT gate driver 126. For example, the allowed input voltagerange of GaN JFET 124 may be from −3V to +3V. Thus, existing IGBT gatedrivers may not be suitable for use in driving GaN JFET 124.Accordingly, embodiments of the present invention utilize GaN JFETdriver 122 to facilitate use of an IGBT gate driver 126 with GaN JFET124.

FIG. 2 is a simplified schematic diagram illustrating elements of a GaNtransistor circuit according to an embodiment of the present invention.Referring to FIG. 2, the GaN JFET driver 122 may include severalcomponents. The GaN JFET driver 122 may include a bias voltage generatorcircuit 210, a supplementary JFET transistor 220, and output driver 230.In some embodiments of the invention, the GaN JFET driver 122 mayinclude a current/V_(ds) (drain to source voltage) monitoring circuit240 to monitor the drain to source current and voltage of thesupplementary transistor 220. According to embodiments of the invention,the supplementary transistor 220 may be a GaN JFET transistor. Inanother embodiment, the supplementary transistor 220 can be a siliconJFET.

The drain of the main GaN JFET 124 can be tied to the drain of thesupplementary transistor 220. At node 260 and 264, high and low gatedrive levels, respectively, are generated by the bias voltage generatorcircuit 210 and coupled to the output driver 230. In one embodiment, thehigh and low gate drive levels may be +3V and −3V, respectively. Theoutput driver 230 also receives the power signal from the external IGBTgate driver at node 262, which is also one of the three terminals, A2,of the three terminal GaN transistor circuit 120. As such, an outputvoltage from the IGBT driver 126 of FIG. 1( b), e.g., a +15/−15 Vsignal, may be also fed as an input to the output driver 230.

The input voltage at node 262 (e.g. +15/−15 V) can act as a timingsignal to the output driver 230 to generate a reduced voltage (e.g.+3/−3 V) output at node 266 to the gate of main JFET 124. Thus, anoutput drive voltage from the output driver may be characterized by alower amplitude than the input voltage. Since the drain of thesupplementary transistor 220 is tied to the drain of the main transistor124, the output driver 230 is powered by the voltage present on thedrain terminal B2 of JFET 124. Therefore, GaN transistor circuit 120does not require a separate power terminal, so it can be realized withonly three terminals.

Referring to FIG. 2, an example optional current/V_(ds) monitoringcircuit 240 is illustrated. The current monitoring circuit 240 maymonitor the current through main JFET 124 and provide a control signalto output driver 230 which can then provide overcurrent protection formain JFET 124. The current monitoring circuit 240 is coupled to thesource of the supplementary transistor 220. When the voltage on thedrain of the main JFET 124 is lower than the pinch-off voltage ofsupplementary JFET 220 (e.g. 20-40V), and there is little current flowthrough supplemental JFET 220 (e.g. less than 1 mA), the voltages at thedrain and the source of the supplemental JFET 220 are almost the same.Therefore, the voltage on the source of supplemental JFET tracks thedrain voltage of the main JFET 124, which is related to the currentthrough main JFET 124 by the on-resistance of main JFET 124.

The voltage on the source of supplemental JFET 220 thus represents thecurrent flowing through JFET 124 and serves as an input to currentmonitoring circuit 240. In one embodiment, current monitoring circuit240 may comprise a circuit that compares the voltage on the source ofsupplemental JFET 220 with a predetermined reference voltage andprovides a signal to output driver 230 when the source voltage exceedsthe reference voltage (signifying that the current flowing through mainJFET 124 has exceeded a predetermined value). Output driver 230 may thenturn off the main JFET 124 to provide a current limit function. In someembodiments there may be a capacitor 250 to operatively couple the biasvoltage generator circuit 210 and output driver 230 to ground atterminal C2.

FIG. 3 is an exemplary schematic diagram illustrating devices suitablefor use in elements of a GaN transistor circuit according to anembodiment of the present invention. In the embodiment shown in FIG. 3,the current monitoring circuit 240 of FIG. 2 is optional as illustrated.In FIG. 3, the bias voltage generator circuit 210 may receive an inputvoltage from a voltage source V3 300, which may be a pulse signal of+15/−15 V. The pulse voltage source V3 300 may be coupled in series witha resistor R10 302 which is typical 100 ohms. The bias voltage circuit210 shown may be comprised of diode D1 306 and diode D2 304 in parallelwith each other and further operatively coupled to in series withcapacitor C3 308 and capacitor C4 310. For example, C3 308 and C4 310may have a capacitance of 2 nF each.

The bias voltage generator circuit 210 may also comprise a linearvoltage regulators 312 and 314 as shown in FIG. 3. The linear voltageregulator 312 is a positive voltage regulator, giving a +5V output wheninput voltage is between +7V and +15V. The positive voltage regulator312 may include a BJT Q3 346 and BJT Q4 348. Additionally, the positivelinear voltage regulator 312 can include resistors R11 350, R12 348, andR13 350, each with a value of 1 k Ω, for example. Zener diodes may alsobe included, for example Zener diodes D3 352 with a breakdown voltage of5.1 V and D4 354 with a breakdown voltage of 2.5 V. Zener diodes canoperate like ideal diodes in allowing current to flow from the anode tothe cathode, but unlike ideal diodes, Zener diodes have a breakdownvoltage at which current is allowed to flow in a reverse direction.

Linear voltage regulator 314 is a negative voltage regulator, giving a−5V output when input voltage is between −7V and −15V. The negativevoltage regulator 314 may include a BJT Q5 362 and BJT Q6 364. Otherelements in the negative linear voltage regulator 314 can also includeresistors R14 368, R15 372, and R16 370, each with a value of 1 k Ω forexample. Zener diodes may also be included the negative linear voltageregulartor 314, for example Zener diodes D5 366 with a breakdown voltageof 5.1 V and D6 364 with a breakdown voltage of 2.5 V. Additionally, thebias voltage circuit 210 may include resistors R3 316 and R4 322, eachhaving a resistance of, for example, 10 mΩ. Each resistor may be inseries with a capacitor. Resistor R3 316 may be in series with capacitorC5 318, having an exemplary value of 10 nF. Resistor R4 322 may be inseries with capacitor C6 320, having an exemplary value of 10 nF.Accordingly, the bias voltage generator circuit 210 receives a pulsesignal and biases the voltage to a lower pulse signal; for example, thebias voltage generator circuit 210 may receive an input pulse signalfrom voltage source V3 300 of +15/−15 V and generate an output of +5/−5V.

Coupled to the bias voltage generator circuit 210 to receive the biasedoutput voltage (e.g., +5/−5 V) may be an output driver circuit 230. Theoutput driver circuit 230 may include two BJT transistors 328 and 330.The input pulse signal from voltage source 300 can be coupled to thegates of transistors 328 and 330 via resistors 324 and 326,respectively. Resistors 324 and 326 may be exemplary values of 10Ω each.The BJTs 328 and 330 may be coupled in series, with the drain of BJT 328coupled to the +5 V of the biased output voltage from the bias voltagegenerator circuit 210, and the drain of BJT 330 may be coupled to the −5V of the biased output voltage from the bias voltage generator circuit210.

Outside of the output driver circuit 230, a capacitor C8 334 with anexemplary value of 100 nF may ground the drain of BJT 330. The drain ofBJT 328 may be grounded via capacitor 334. Capacitor C8 334 can serve asa bypass capacitor, providing low impedance for the driver voltagesduring switching. Bypass capacitors can also include low equivalentseries resistance (ESR) ceramic capacitors.

In an example, capacitor 334 may have a value of 100 nF. The outputdriver 230 may generate an output from the source of BJT 328 and thesource of BJT 320. Thus, BJT 328 and BJT 320 may alternate in turning onand off to generate the output driver 230 output signal that pulses+5/−5 V. Additionally, there may be a current/V_(ds) monitoring circuit240 to monitor the drain to source current and voltage of asupplementary transistor 220. According to embodiments of the invention,the supplementary transistor 220 may be a GaN JFET transistor. ResistorsR17 374 may be coupled in series with resistor R18 to provide a voltagethe gate of supplementary transistor 220. Example values of theresistors R17 374 and R18 376 may be around 100 kΩ.

The current monitoring circuit 240 is coupled to the source of thesupplementary transistor 220, and can include BJT Q7 380, BJT Q8 384,and BJT Q9 381. Additionally, the current monitoring circuit 240 caninclude resistor R20 386, with an example value of 5.2Ω. Therefore, thevoltage on the source of supplemental JFET tracks the drain voltage ofthe main JFET 124, which is related to the current through main JFET 124by the on-resistance of main JFET 124. The voltage on the source ofsupplemental JFET 220 thus represents the current flowing through JFET124 and serves as an input to current monitoring circuit 240. The sourceof supplementary transistor 220 may be coupled to resistor R19 378,having an example value of 1 MΩ.

The generated output from output driver 230 can be coupled to the gateof main JFET 124. The drain of main JFET 124 may be coupled to a directcurrent (DC) voltage source 340 via resistor 336. The drain of main JFET124 may be coupled to the current monitoring circuit 240 via a diode D7388 to prevent current from flowing in the wrong direction. The resistor336 may have an exemplary value of 200Ω. The voltage source 340 mayoutput a DC voltage of 400 V, for example.

In embodiments of the invention, an electronic circuit comprising a GaNJFET transistor 124 and a GaN JFET driver 122 may be integrated in thesame package. However, they may not be comprised of the same material oron the same die.

The GaN JFET driver 122 of the present invention has several advantagesand benefits. For example, because of characteristics of the GaN JFETdriver 122, a certain voltage amplitude may be received as an input(e.g., +15/−15 V) and then a different voltage amplitude is generated asan output (e.g., +5/−5 V). Accordingly, the GaN JFET driver 122 mayoperate a voltage converter that is self-driven since it can operatewithout an external power supply. The GaN JFET driver 122 may be drivenoff the voltage that is given to the gate and the drain of the main JFET124, thereby eliminating the need for an external power supply.

Voltage converter circuits can be configured in a buck topologyutilizing external inductors, capacitors and other components. However,in embodiments of the present invention, the voltage converter circuits,for example, the bias voltage generator circuit 210 and output drivercircuit 230, can be configured as integrated circuits that use the powerfrom the drain of the GaN JFET 124 to power the GaN JFET driver 122. Asa result, embodiments of the present invention reduce or eliminate thenumber of power supplies utilized as well as, potentially, otherexternal components.

FIG. 5 illustrates an exemplary simulation of the circuit shown in FIG.3. The graph at 502 shows the input pulse voltage of voltage source V3300. As can be seen, the input voltage V3 300 is pulsed between +15 Vand −15 V. 504 shows the gate voltage of the main JFET 124, and in thesimulation example, pulses between +5 V and −5 V. 506 shows the voltageacross the drain to source of main JFET 124. In this example, the Vds ofmain JFET 124 shown in graph 506 pulses between 0 V and 400 V. Graph 508shows the drain to source current of the main JFET 124 (Ids), which isshown to alternate between 0 A and 2 A.

FIG. 4 is a simplified flowchart illustrating a method of operating anIGBT gate driver in conjunction with a GaN transistor according to anembodiment of the present invention. As illustrated, the electroniccircuits discussed herein enable GaN electronics to be utilized asdrop-in replacements for IGBTs. The method of operating a GaN JFET caninclude providing the GaN JFET at 400, and receiving an input voltagefrom an IGBT gate driver, as shown at 402. The input voltage can be apulsed input voltage, for example, +15/−15 V. The method can alsoinclude, at 403, deriving power from the drain terminal of the GaNtransistor and generating high and low gate drive levels as shown at404.

The high and low gate drive levels are generated by a bias voltagegenerator circuit in a GaN JFET driver. The GaN JFET driver may includea supplementary transistor coupled to the bias voltage generatorcircuit, further coupled to an output driver. The biased input voltagemay be in a smaller range or amplitude than the input voltage, forexample, +3/−3 V, which is within the safe operating range of the gateof the GaN JFET.

In other embodiments, a current monitoring circuit may be coupled to thesupplementary transistor and the output driver. Accordingly, the methodcan include, as shown at 406, monitoring a current through the GaNtransistor and providing a current limit signal when the current exceedsa predetermined value. In some embodiments, the supplementary transistormay be a GaN FET.

The method can further include receiving, at an output driver, the highand low gate drive levels, the current limit signal, and the inputvoltage at 408. These inputs are used by the output driver to generatean output signal.

In 410, the method may also comprise generating an output signal basedon the high and low gate drive levels, the current limit signal, and theinput voltage. The output signal from the output driver can then be usedto drive the gate of the GaN transistor (e.g., JFET) by providing theoutput signal to the gate of the GaN JFET, as in 412. The output drivevoltage can be characterized by a lower amplitude than the inputvoltage.

For example, the output drive voltage can be +3/−3 V compared to +15/−15V of the input voltage.

In some embodiments, the method may further comprise packaging thedriver and the main transistor in a same package. The driver and themain transistor can be co-packaged on different dies. For example, theGaN JFET driver and the main JFET transistor may be co-packagedtogether, but on different dies.

It should be appreciated that the specific steps illustrated in FIG. 4provide a particular method of operating a GaN transistor circuitaccording to an embodiment of the present invention. Other sequences ofsteps may also be performed according to alternative embodiments. Forexample, alternative embodiments of the present invention may performthe steps outlined above in a different order. Moreover, the individualsteps illustrated in FIG. 4 may include multiple sub-steps that may beperformed in various sequences as appropriate to the individual step.Furthermore, additional steps may be added or removed depending on theparticular applications. One of ordinary skill in the art wouldrecognize many variations, modifications, and alternatives.

It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this applicationand scope of the appended claims.

1-19. (canceled)
 20. An electronic circuit comprising: a first driverconfigured to generate an input voltage; a second driver coupled to thefirst driver, the second driver configured to receive the input voltageand generate a drive voltage based on the input voltage; and a galliumnitride (GaN) transistor having a gate, a drain, and a source, whereinthe gate is coupled to the second driver, and configured to receive thedrive voltage.
 21. The electronic circuit of claim 20, wherein thesecond driver comprises: a bias voltage generator configured to receivethe input voltage and generate a biased voltage output based on theinput voltage; a supplementary transistor coupled to the bias voltagegenerator; and an output driver configured to: receive the biasedvoltage output from the bias voltage generator; receive the voltageinput from the first driver; and output the drive voltage.
 22. Theelectronic circuit of claim 21, wherein the supplementary transistorcomprises a gate, a drain, and a source, wherein: the gate of thesupplementary transistor is coupled to the biased voltage output of thebias voltage generator; and the source of the supplementary transistorprovides a current to the bias voltage generator.
 23. The electroniccircuit of claim 22, wherein the drain of the GaN transistor is coupledto the drain of the supplementary transistor.
 24. The electronic circuitof claim 22, wherein the supplementary transistor is a transistor formedof GaN, such that: the drain of the supplementary transistor comprises aGaN substrate and a drain contact; the source of the supplementarytransistor is separated from the GaN substrate by a drift region andcomprises a source contact; the drift region of the supplementarytransistor comprises a first GaN epitaxial layer coupled to the GaNsubstrate; and the gate of the supplementary transistor comprises asecond GaN epitaxial layer coupled to the first GaN epitaxial layer anda gate contact coupled to the biased voltage output of the bias voltagegenerator.
 25. The electronic circuit of claim 22, the second driverfurther comprising a current monitor configured to detect a current fromthe drain to the source of the supplementary transistor and output aregulated current, wherein the output driver further is configured toreceive the regulated current from the current monitor.
 26. Theelectronic circuit of claim 21, wherein the supplementary transistor andthe gallium nitride transistor are junction gate field-effecttransistors.
 27. The electronic circuit of claim 21, wherein the outputdriver is a voltage converter.
 28. The electronic circuit of claim 20,wherein the second driver is driven by a voltage at the drain of thegallium nitride transistor.
 29. The electronic circuit of claim 20,wherein the second driver and the gallium nitride transistor areco-packaged in a same package.
 30. The electronic circuit of claim 29wherein the second driver and the gallium nitride transistor are ondifferent dies.
 31. The electronic circuit of claim 20, wherein thefirst driver is an insulated-gate bipolar transistor (IGBT) driver andthe second driver is a gallium nitride (GaN) junction gate field-effecttransistor (JFET) driver.
 32. The electronic circuit of claim 20,wherein the input voltage is greater than the drive voltage.
 33. Amethod of operating a gallium nitride (GaN) junction gate field-effecttransistor (JFET), the method comprising: receiving, at a GaN JFETdriver, an input voltage; generating, by the GaN JFET driver, a biasedvoltage output based on the input voltage; and providing, by the GaNJFET driver, an output drive voltage to the GaN JFET, wherein the outputdrive voltage is based on the biased voltage output.
 34. The method ofclaim 33, further comprising: monitoring a current of a supplementarytransistor to provide a current value; receiving, at an output driver,the biased voltage output, the current value, and the input voltage; andgenerating the output drive voltage based on the biased voltage output,the current value, and the input voltage.
 35. The method of claim 34wherein the current value is based on the current from the drain to thesource of the supplementary transistor.
 36. The method of claim 33wherein the input voltage comprises a pulsed input voltage.
 37. Themethod of claim 33 wherein the output drive voltage is characterized bya lower amplitude than the input voltage.
 38. The method of claim 33wherein the output drive voltage is generated by a voltage converter.39. The method of claim 38 wherein the voltage converter is driven by avoltage at a drain of the GaN JFET.